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FPGA Module
IDN Komponenten
StageMate ISP
StageFeed ISP
NetBridge ISP
MetaMorph CPU
Laser Projektoren
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Binaries (FPGA configuration, operating system and firmware) targeting a Xilinx Spartan-6 (XC6SLX25-2FTG256C) FPGA. The system has a versatile licensing mechanism for all software and hardware modules. This mechanism allows for cost-efficient and application-oriented use of options and features.

The core can be used in any custom FPGA-System that complies to the component and pinout specification. The included firmware is based on a modular library design to be used in different scenarios. Hardware and pin configuration are stored in a configuration EEPROM, hardware and firmware features are enabled through the license file located along with the FPGA configuration and the firmware binaries in the system ROM.


Management and Update Tool (NetView) - Java program located inside the zip file.

Firmware Bundle

System Features

  • User provided device name and icon for easy identification, unique unit ID.

  • User reset, sets defaults for common parameters such as networking for easy retrieval in case of misconfiguration.

  • Monitor dialog through 115kBaud UART and Telnet.

  • Powerful configuration parameter dictionary.

  • LwIP 1.4.1 with Ethernet and SLIP drivers, performant multithreading architecture.

  • System profiler.

  • Embedded System Administration (ESA) server.

  • Single file bundle (zip archive) for distribution.

IDN Server Module

  • Sophisticated timeline reassembly and tracking algorithm with jitter compensation and automatic latency adaption.

  • Fast and efficient zero-copy network buffer management.

  • Server implementation derived from object oriented and device independent IDN library.

  • Detailed packet statistics.

IDN Bridge Module

  • Plug and play. Automatic setup and teardown of bridges through network probes.

  • Ability to scan the network for compatible receivers, store the list in nonvolatile memory and build bridges. The scan works for directly connected devices or across switches.

  • Supports configured, self initiated bridges and externally initiated bridges to be used with monitors and recorders.

  • Receiver configuration through UnitID and IP-Address to support dynamic address assignments and static assignments behind routers.

  • ISP signal splitter, support for 2 further receivers (total of 3) for signal duplication or multiplication (more in preparation).

  • Additional drain for remote host initiated brides for monitoring or recording.

Laser Projector Output Core

  • Single head and dual head operation with independent timing.

  • Flexible frequency synthesizer with a resolution of 250nS. The synthesizer allows for precise playback frequency match and detune needed by latency adaption.

  • Timeshifts for intensity and color (based on galvo command, known as colorshift) and color lines (based on intensity, introduced as color line tweaking).

  • Timeshifts between signals are configured in units of microseconds with a resolution of 250 nanoseconds. This keeps the shifts stable for all sample frequencies.

  • DAC output calibration (gain and offset).

  • Maximum throughput of 250.000 samples per second, full resolution, all channels.

DMX512 Output Core

  • Byte stream implementation allows for arbitrary start codes or stray custom data mixed with DMX512 data.

  • Large hardware FIFO reduces CPU attendance.

  • Commands for idle (all one) and break (all zero) characters.

ISP (ILDA Standard Projector) Input Core

  • Fully implemented ISP-Port (X, Y, I, R, G, B, U1, U2, U3, U4, Shutter, Interlock).

  • Interlock check through oscillator and edge detection.

  • Calibration for all inputs (offset and gain) in hardware.

DMX512 Input Core

  • Jabber detection and indication.

  • Large hardware FIFO reduces CPU attendance.

Ethernet Core

  • Performance optimized MAC core and driver software. Zero copy buffer management.

  • PHY-Level peer detection protocol.

FPGA Signals

Basic core and CPU signals

CLK25T825 MHz system clock, ± 25ppm
UART_LOG_TXC8Console log (115 kBaud, 8Bit, 1Stop, no parity). StageCore1 uses this UART to send runtime log messages.
UART_MON_RXA9User monitor dialog (115 kBaud, 8Bit, 1Stop, no parity)
UART_MON_TXC9User monitor dialog (115 kBaud, 8Bit, 1Stop, no parity)
DLED<0>E4Boot error code LED (red, high = on, low = off)
DLED<1>F5Boot error code LED (red, high = on, low = off)
DLED<2>N4Boot error code LED (red, high = on, low = off)
DLED<3>B3Boot error code LED (red, high = on, low = off)
TEST<0>N9CPU test pin (optional)
TEST<1>P9CPU test pin (optional)
TEST<2>R9CPU test pin (optional)
TEST<3>T9CPU test pin (optional)
TEST<4>M9CPU test pin (optional)
TEST<5>N8CPU test pin (optional)

QSPI Flash ROM (8MB, Winbond W25Q64FVSSIG or compatible)

QSPI_CST3Chip select

RMII PHY (Micrel KSZ8021RNL or compatible)

RMII_CLKL13RMII clock output
RMII_RXD<0>T13Receive data input [0]
RMII_RXD<1>R12Receive data input [1]
RMII_RX_ERH11Receive error input
RMII_CRS_DVF12Carrier sense / Receive data valid input
RMII_TXD<0>H13Transmit data output [0]
RMII_TXD<1>H14Transmit data output [1]
RMII_TX_ENE12Transmit enable output
MII_MDCT12Management interface (MII) clock output
MII_MDIOL12Management interface (MII) data I/O
ETH_PHY_RST_NG11PHY reset output, active low, needs external 4k7 pulldown
ETH_PHY_IRQ_NE13PHY interrupt input, active low
ETH_PEER_LEDP11Peer LED (low = on, Z = off)

System status

READYM6System ready condition (everything up and running). Can be used in a condition to open an interlock.
ERROR_LEDT14Error LED (red, low = on, Z = off)
SESSION_LEDL14Session LED (blue, low = on, Z = off), this LED is controlled by the IDN server and signals an active session.
BRIDGE_LEDL16Bridge LED (blue, low = on, Z = off), this LED is controlled by the feed client and signals an active bridge.
MATE_STATUS1_LEDP15Mate status LED (green, low = on, Z = off)
MATE_STATUS2_LEDP16Mate status LED (green, low = on, Z = off)
FEED_STATUS1_LEDR14Feed status LED (green, low = on, Z = off)
FEED_STATUS2_LEDT15Feed status LED (green, low = on, Z = off)
PUSH_BUTTONT7Push button used for communication/firmware reset and pairing


A 24C64 type EEPROM (or compatible) shall be reachable at address 0xA8

IIC_SCLP4Needs external pullup
IIC_SDAT4Needs external pullup

Laser projector: Common converter signals

CV_CLK1C10DAC clock output (galvo, laser, color)
CV_CLK2C416 Bit ADC clock output
CV_CLK3F712 Bit ADC clock output

Laser projector: Galvo commands and feedback

Converters used: AD5662xRJ-2 or compatible

G1C_CSB5Port 1 galvo chip select output
G1CX_DA5Port 1 galvo X output (ISP out: X)
G1CY_DB6Port 1 galvo Y output (ISP out: Y)
G2C_CSH15Port 2 galvo chip select output
G2CX_DH16Port 2 galvo X output (ISP out: U4)
G2CY_DJ14Port 2 galvo Y output

Laser projector: Laser commands and feedback

The timing of these signals is referenced to the galvo signals (Blankshift). Converters used: DAC7311IDCK or compatible

L1_CLRD6Port 1 laser clear output (ISP out: Shutter). This signal indicates the intention of laser emission (low = dark, high = emission).
L1C_CSC6Port 1 chip select output
L1C_DB10Port 1 data output (ISP out: Intensity)
L2_CLRB14Port 2 laser clear output. This signal indicates the intention of laser emission (low = dark, high = emission).
L2C_CSA14Port 2 chip select output
L2C_DD11Port 2 data output

Laser projector: Color line commands

The timing of these signals is referenced to the laser control signals and can be individually tweaked. Converters used: DAC7311IDCK or compatible

A1_CSC7Port 1 line A chip select output
A1_DA7Port 1 line A data output (ISP out: R)
B1_CSD5Port 1 line B chip select output
B1_DC5Port 1 line B data output (ISP out: G)
C1_CSF9Port 1 line C chip select output
C1_DD9Port 1 line C data output (ISP out: B)
D1_CSE7Port 1 line D chip select output
D1_DE8Port 1 line D data output
A2_CSF13Port 2 line A chip select output
A2_DF14Port 2 line A data output (ISP out: U1)
B2_CSG14Port 2 line B chip select output
B2_DG16Port 2 line B data output (ISP out: U2)
C2_CSJ13Port 2 line C chip select output
C2_DK14Port 2 line C data output (ISP out: U3)
D2_CSJ11Port 2 line D chip select output
D2_DJ12Port 2 line D data output

Laser projector: Other signals

ISP_DMX_OUTP5DMX512 output according to ISP-DMX standard

Laser projector: ILDA Standard Projector (ISP) input

Converters used: ADS8326(16 Bit) and ADS7866(12 Bit) or compatible

ISP_CS16D1416 bit converter chip select output
ISP_CS12D1112 bit converter chip select output
ISP_XD12X converter data input (16 Bit)
ISP_YA14Y converter data input (16 Bit)
ISP_IL10I converter data input (12 Bit)
ISP_RM15R converter data input (12 Bit)
ISP_GM10G converter data input (12 Bit)
ISP_BM16B converter data input (12 Bit)
ISP_U1E6U1 converter data input (12 Bit)
ISP_U2A4U2 converter data input (12 Bit)
ISP_U3N5U3 converter data input (12 Bit)
ISP_U4D8U4 converter data input (16 Bit)
ISP_CLRB14Shutter input
ISP_ITXE15Interlock transmit output
ISP_IRXE16Interlock receive output
ISP_DMX_INT5DMX512 input according to ISP-DMX standard